1) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for planarizing an insulating interlayer to be used in conjunction with other multilevel interconnect technology.
2) Description of the Prior Art
To manufacture an integrated circuit, it is necessary to form many active devices on a single substrate. Initially, each of the devices must be isolated from the others, but recently it has become necessary to electrically interconnect specific devices during the fabrication step to obtain the desired functionality of the circuit. Both MOS and bipolar devices have multilevel interconnect structures to accommodate the numerous interconnections of the devices.
As the number of layers in an interconnect structure increase, the topography of the top layer coated on the semiconductor wafer becomes more rugged. For example, in manufacturing a semiconductor wafer having two or more metal layers formed thereon, a first insulating interlayer is coated on the wafer on which a plurality of oxide layers, polycrystalline silicon conductive layers and a first metal wiring layer, have been previously formed, followed by forming vias for interposing a second metal layer. The surface of the first insulating layer is uneven because the underlying structure which the first insulating layer has was formed upon is uneven. When a second metal layer is directly formed over such a first insulating interlayer, the metal lines of the second layer may short to each other due to poor photo resolution on the uneven surface and because metal stringers of the second metal layer remain in the gaps of two metal lines of the first metal layer. This failure lowers the yield of the semiconductor device. Therefore, planarization of the insulating interlayer is required for multilevel metal interconnections, before forming a via or coating a second metal layer.
One of the simplest methods available for planarizing the semiconductor wafer having steps formed thereon is to deposit a chemical vapor deposition (CVD) glass layer which is significantly thicker than the step height it must cover. However, this is unrealistic because increasing the thickness of the insulating layer also increases the via depth between a first metal wiring layer and a second metal layer. Furthermore, as the first metal wiring layers become more closely packed, voids will form in the insulating layer if conventional CVD-SiO2 processes are used.
One conventional planarization method is to form an insulating layer includes using a resist layer coated on an insulating interlayer as a sacrificial layer. The process comprises coating a resist layer and etching back the insulating interlayer by using the resist layer as a sacrificial layer to adjust the thickness of the insulating interlayer.
In the next step, the sacrificial resist layer is first rapidly etched back by dry etching until the topmost regions of the insulating interlayer are just barely exposed. The etch chemistry is then modified so that the sacrificial layer material and the insulating interlayer material are etched at approximately the same rate. Etching continues under these conditions until all of the sacrificial resist layer has been etched away. By this etch-back procedure, the surface of the insulating interlayer is highly planarized since the profile of the sacrificial layer is thus transferred to the insulating interlayer. In some cases, the thickness of the insulating interlayer over underlying metal layers may be thinner than desired after the etch-back step is completed. In other cases, etch-back is allowed to proceed until the first metal wiring layers are exposed for improving the degree of planarization. In such a case, an additional CVD insulating layer is generally deposited in order to establish the minimum adequate thickness of the insulating interlayer.
As the integration density of semiconductor/devices increases, the spaces between the metal layers become narrower. Therefore, various problems such as the formation of voids in the insulating interlayer occur, so its planarization becomes difficult to improve. To improve the degree of planarization of the insulating layer formed over such closely spaced metal layers, a method of repeating the etch-back step two times has been typically carried out. However, the conventional two step etch back process does not adequately solve the problem of void formation in the first dielectric layer.
Another dielectric planarization scheme involves spin-on-glass (SOG) dielectric material. Spin-on-glass is a smoothing dielectric applied by spin coating that fills the spaces in the smaller geometries. When thin layers of SOG in the range of 1000 .ANG. and thicker are used a chemical vapor deposition (CVD) dielectric is needed to form the isolation between the SOG layer and the underlying metal layers.
As a result of several problems, such as adhesion loss and degradation of film stability, a sandwich scheme with a layer of SOG encapsulated between two layers of CVD dielectric is effective in obtaining planarization without the problems exhibited by a single layer of CVD and a single layer of SOG. The bottom dielectric layer serves as an adhesion and hillock suppresser layer and should prevent the SOG from coming in contact with the metal. SOG is the middle layer and serves primarily as the planarization layer. Finally a top CVD dielectric serves as an isolation layer.
This three level sandwich structure has several drawbacks. First, voids in the first dielectric layer are still formed between closely spaced metal lines. Particularly, when the spacing between the metal lines is less than twice the first dielectric layer thickness. These voids in the first dielectric layer are covered over by the middle SOG layer and the second dielectric layer.
Second, via poisoning occurs in the vias where the SOG layer touches the metal contacts. Where the spin-on-glass layer contacts the metal contacts in via holes, moisture from the spin-on-glass layer attacks the metal contact causing electrical failures.
Several patents have attempted to improve the SOG sandwich structure process by using a double SOG layer etch back process. This process begins by forming a first dielectric layer and a first SOG layer. Then the first SOG layer can be etched back. After this, a second SOG layer and a second dielectric layer is formed over the first SOG layer.
The following patents teach some variations on this process: KIM, U.S. Pat. No. 5,296,092 (uses 3 dielectric layers and 2 SOG layers), Hawley et al. U.S. Pat No. 5,308,795 (Uses the metal layer as an etch back stop), Grewal et. al., U.S. Pat. No. 5,212,114 and Chen et al. U.S. Pat. No. 5,250,472 (etches back a first SOG layer but does not etch back the second SOG layer). However, these process do not adequately solve the above problems of the voids, via poisoning and adequate planarization.
It is desirable to develop a planarization process which provides void-free planarization layers between conductive lines, provides improved planarity and reduces poison via problems